A high thermal stability ohmic contact for GaN-based devices.

Co-integration of gallium nitride (GaN) power devices with Si logic ICs provides a way of applying high power and high efficiency circuits on a single chip. In order to co-integrate GaN devices with Si ICs, an ohmic contact for GaN devices has to be Si compatible and durable at the same or higher temperature of the back-end process in the conventional complementary metal oxide semiconductor (CMOS) industry. In this work, an Au-free ohmic junction with high thermal stability for AlGaN/GaN high electron mobility transistors (HEMTs) was presented. The proposed titanium nitride (TiN) contacts on AlGaN/GaN HEMTs retained their ohmic characteristics and stayed stable at temperatures even higher than 1000 °C. The interface chemistry analysis using STEM EELS revealed the enhancement of the binding energy of Ga-N and Al-N and invisible diffusion of Ti during treatment below 1000 °C. This clarifies the origin of the highly stable ohmic contact. Thus, our work provides a new pathway and thought for forming reliable contacts for HEMTs or another GaN-based devices.

Single-Gate In-Transistor Readout of Current Superposition and Collapse Utilizing Quantum Tunneling and Ferroelectric Switching.

In nanostructure assemblies, the superposition of current paths forms microscopic electric circuits, and different circuit networks produce varying results, particularly when utilized as transistor channels for computing applications. However, the intricate nature of assembly networks and the winding paths of commensurate currents hinder standard circuit modeling. Inspired by the quantum collapse of superposition states for information decoding in quantum circuits, the implementation of analogous current path collapse to facilitate the detection of microscopic circuits by modifying their network topology is explored. Here, the superposition and collapse of current paths in gate-all-around polysilicon nanosheet arrays are demonstrated to enrich the computational resources within transistors by engineering the channel length and quantity. Switching the ferroelectric polarization of Hf0.5 Zr0.5 O2 gate dielectric, which drives these transistors out-of-equilibrium, decodes the output polymorphism through circuit topological modifications. Furthermore, a protocol for the single-electron readout of ferroelectric polarization is presented with tailoring the channel coherence. The introduction of lateral path superposition results into intriguing metal-to-insulator transitions due to transient behavior of ferroelectric switching. This ability to adjust the current networks within transistors and their interaction with ferroelectric polarization in polycrystalline nanostructures lays the groundwork for generating diverse current characteristics as potential physical databases for optimization-based computing.

Advanced Cu chemical displacement technique for SiO2-based electrochemical metallization ReRAM application.

This study investigates an advanced copper (Cu) chemical displacement technique (CDT) with varying the chemical displacement time for fabricating Cu/SiO2-stacked resistive random-access memory (ReRAM). Compared with other Cu deposition methods, this CDT easily controls the interface of the Cu-insulator, the switching layer thickness, and the immunity of the Cu etching process, assisting the 1-transistor-1-ReRAM (1T-1R) structure and system-on-chip integration. The modulated shape of the Cu-SiO2 interface and the thickness of the SiO2 layer obtained by CDT-based Cu deposition on SiO2 were confirmed by scanning electron microscopy and atomic force microscopy. The CDT-fabricated Cu/SiO2-stacked ReRAM exhibited lower operation voltages and more stable data retention characteristics than the control Cu/SiO2-stacked sample. As the Cu CDT processing time increased, the forming and set voltages of the CDT-fabricated Cu/SiO2-stacked ReRAM decreased. Conversely, decreasing the processing time reduced the on-state current and reset voltage while increasing the endurance switching cycle time. Therefore, the switching characteristics were easily modulated by Cu CDT, yielding a high performance electrochemical metallization (ECM)-type ReRAM.

Improvement in pH sensitivity of low-temperature polycrystalline-silicon thin-film transistor sensors using H2 sintering.

In this article, we report an improvement in the pH sensitivity of low-temperature polycrystalline-silicon (poly-Si) thin-film transistor (TFT) sensors using an H2 sintering process. The low-temperature polycrystalline-silicon (LTPS) TFT sensor with H2 sintering exhibited a high sensitivity than that without H2 sintering. This result may be due to the resulting increase in the number of Si-OH2(+) and Si-O(-) bonds due to the incorporation of H in the gate oxide to reduce the dangling silicon bonds and hence create the surface active sites and the resulting increase in the number of chemical reactions at these surface active sites. Moreover, the LTPS TFT sensor device not only offers low cost and a simple fabrication processes, but the technique also can be extended to integrate the sensor into other systems.

Low-temperature poly-Si nanowire junctionless devices with gate-all-around TiN/Al2O3 stack structure using an implant-free technique.

In this work, we present a gate-all-around (GAA) low-temperature poly-Si nanowire (NW) junctionless device with TiN/Al.